Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (“IC's”).
Several steps are common to most design flows. Initially, a design may typically start at a high level of abstraction, by a designer creating a specification that describes particular desired functionality. This specification, often implemented by a programming language, such as, for example, the C or C++ programming language, describes at a high level the desired behavior of the device. Designers will then typically take this specification for the design and create a logical design, often implemented in a netlist, through a synthesis process. The logical design describes the individual components of the design, and also may have different level of abstraction, such as, for example the gate level or the register level.
A register transfer level (“RTL”) design, often implemented by a hardware description language (“HDL”) such as Verilog, SystemVerilog, or Very High speed hardware description language (“VHDL”), describes the operation of the device by defining the flow of signals or the transfer of data between various hardware components within the design. More particularly, a register transfer level design describes the interconnection and exchange of signals between hardware registers and the logical operations that are performed on those signals.
Typically, a register transfer level design is first synthesized from the specification, followed by a gate level design being synthesized from the register transfer level design. Gate level designs describe the actual physical components such as transistors, capacitors, and resistors as well as the interconnections between these physical components. Often, gate level designs are also implemented by a netlist, such as, for example, a mapped netlist. Lastly, the gate-level design is taken and another transformation is carried out. First by place and route tools that arrange the components described by the gate-level netlist and route connections between the arranged components; and second, by layout tools that generate a layout description having layout “shapes” that may then used to fabricate the electronic device, through for example, an optical lithographic process.
Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (“GDSII”) format is popular for transferring and archiving two-dimensional graphical IC layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Mentor Graphics, Inc., and the more recent Open Artwork System Interchange Standard (OASIS) proposed by Semiconductor Equipment and Materials International (“SEMI”). These various industry formats are used to define the geometrical information in integrated circuit layout designs that are employed to manufacture integrated circuits. Once the microcircuit device design is finalized, the layout portion of the design can be used by fabrication tools to manufacturer the device using a photolithographic process.
There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.
Each time that a layer of material is exposed to radiation, a mask must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in layout design data define the relative locations or areas of the circuit device that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the layout design data, after which the mask can be used in a photolithographic process. The image embodied in the layout data is often referred to as the intended or target image or target contours, while the image created in the mask is generally referred to as the mask contours. Furthermore, the image created on the substrate by employing the mask in a photolithographic process is often referred to as the printed image or printed contours.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate become smaller and are placed closer together. The feature sizes are often referred to by the distance between features, conventionally called the “process step,” or the “node.” For example, one nod is the 32 nanometer (“nm”) node. This implies that adjacent features in the design, such as, for example, identical cells in a memory array, are 32 nanometers apart. As process steps are continually scaled down, the corresponding reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. Various common techniques exist for mitigating these pattern dependant effects. These techniques are commonly referred to as “resolution enhancement techniques” or “RETs.” For example, optical process correction (“OPC,”) douple patterning, and “assist features” (i.e. features inserted into a mask that are not intended to be replicated during the manufacturing process, but which increase the fidelity of the image) are a few common resolution enhancement techniques (RET) that are often employed to prepare a physical layout designs for manufacturing.
Even though conventional resolution enhancement techniques, such as, for example optical process correction, provide for an increase in image fidelity, this increase in image fidelity may not be sufficient at future nodes. For example, conventional optical process correction limits a particular mask shape to having a one to one comparison to the corrected mask shape. Additionally, the topology of a mask shape corrected by conventional resolution enhancement techniques will have a similar topology to the original mask shape. Furthermore, the inclusion or insertion of assist features into a corrected mask is time consuming and requires significant effort on the part of the designer to facilitate.